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| 1 of 20 features ? temperature measurements require no external components ? measures temperatures from -55c to +125c in 0.03125c increments. fahrenheit equivalent is -67f to +257f in 0.05625f increments ? temperature is read as a 13 -bit value ( two byte transfer) ? converts temperature to digital word in 1 second (max) ? 256 bytes of e 2 memory on board for storing information such as frequency compensation coefficients ? data is read from/written via a 2 - wire serial interface (open drain i/o lines) ? app lications include temperature - compensated crystal oscillators for test equipment and radio systems ? 8- pin dip or soic packages pin assignment pin description sda - 2- wire serial data input/output scl - 2- wire serial clock gnd - gro und a0 - chip address input a1 - chip address input a2 - chip address input v dd - power supply (+2.7v to +5.5v) nc - no connection description the ds1624 consists of a digital thermometer and 256 bytes of e 2 memory. the thermometer provides 13- bit temper ature readings which indicate the temperature of the device. the e 2 memory allows a user to store frequency compensation coefficients for digital correction of crystal frequency due to temperature. any other type of information may also reside in this user space. ds1624 digital thermometer and memory 19 - 6288; r ev 5/12 www.maxim - ic.com 6 3 1 2 4 8 7 5 sda scl nc gnd v dd a 0 a 1 a 2 DS1624S 8 - pin soic (208 mil) 6 3 1 2 4 8 7 5 sda scl nc gnd v dd a 0 a 1 a 2 ds1624 8 - pin pdip (300 mil)
ds1624 2 of 20 ordering information ordering information package marking description ds1624+ ds1624 ds1624 in lead - free 300 mil 8 - pin dip DS1624S+ DS1624S ds1624 in lead - free 208 mil 8 - pin so DS1624S+t&r DS1624S ds1624 in lead - free 208 mil 8 - pin so, 2000 piece tape - and - reel a ?+? symbol will also be marked on the package near the pin 1 indicator. detailed pin description table 1 pin symbol description 1 sda data input/output pin for 2 - wire serial communication port. 2 scl clock input/output pin for 2 - wire s erial communication port. 3 nc no connect. no internal connection. 4 gnd ground pin. 5 a2 address input pin. 6 a1 address input pin. 7 a0 address input pin. 8 v dd supply voltage 2.7v to 5.5v input power pin. overview a block diagram of the ds1624 is shown in figure 1. the ds1624 consists of two separate functional units: 1) a 256? byte nonvolatile e 2 memory, and 2) a direct? to ? digital temperature sensor. the nonvolatile memory is made up of 256 bytes of e 2 memory. this memory may be used to store any type of information the user wishes; for example, frequency compensation coefficients may be placed in this memory to allow for compensation of measured frequency depending upon the temperature at which the measurement is made. these memory locations are accessed through the 2 ? wire serial bus. the direct to digital temperature sensor allows the ds1624 to measure the ambient temperature and report the temperature value in a 13 ? bit word, with 0.03125 c resolution. the temperature sensor and its related registers are accessed through the 2 ? wire serial interface. ds1624 3 of 20 ds1624 functional block diagram figure 1 2- wire serial data bus the ds1624 supports a bi ? directional two ? wire bus and data transmission protocol. a device that sends d ata onto the bus is defined as a transmitter, and a device receiving data as a receiver. the device that controls the message is called a ?master?. the devices that are controlled by the master are ?slaves?. the bus must be controlled by a master device wh ich generates the serial clock (scl), controls the bus access, and generates the start and stop conditions. the ds1624 operates as a slave on the two ? wire bus. connections to the bus are made via the open ? drain i/o lines sda and scl. the following bus prot ocol has been defined (see figure 2): ? data transfer may be initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be inte rpreted as control signals. accordingly, the following bus conditions have been defined: bus not busy: both data and clock lines remain high. start data transfer: a change in the state of the data line, from high to low, while the clock is high, defines a start condition. stop data transfer: a change in the state of the data line, from low to high, while the clock line is high, defines the stop condition. status register & control logic temperature senso r eeprom memory (256 bytes) address and i/o control v dd scl sda a1 a2 a0 gnd ds1624 4 of 20 data valid: the state of the data line represents valid data when, after a start condition, the da ta line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition the number of data bytes transferred between start and stop conditions is not limited, and is determined by the master device. the information is transferred byte ? wise and each receiver acknowledges with a ninth bit. with in the bus specifications a regular mode (100 khz clock rate) and a fast mode (400 khz clock rate) are defined. the ds1624 works in both modes. acknowledge: each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the sla ve. in this case, the slave must leave the data line high to enable the master to generate the stop condition. data transfer on 2 - wire serial bus figure 2 figure 2 details how data transfer is accomplished on the two ? wire bus. depending upon the state o f the r/ w bit, two types of data transfer are possible: 1. data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the slave address. next follows a number of data bytes. the slave returns an acknowledge bit after each received byte. 2. data transfer from a slave transmitter to a master receiver. the first byte (the slave address) is transmitted by the master. the slave then returns an acknowledge bit. next follows a number of data bytes tra nsmitted by the slave to the master. the master returns an acknowledge bit ds1624 5 of 20 after all received bytes other than the last byte. at the end of the last received byte, a ?not acknowledge? is returned. the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the bus will not be released. the ds1624 may operate in the following two modes: 1. slave receiver mode: serial data and clock are received through sda and scl. after each byte is received an acknowledge bit is transmitted. start and stop conditions are recognized as the beginning and end of a serial transfer. addr ess recognition is performed by hardware after reception of the slave address and direction bit. 2. slave transmitter mode: the first byte is received and handled as in the slave receiver mode. however, in this mode the direction bit will indicate that the t ransfer direction is reversed. serial data is transmitted on sda by the ds1624 while the serial clock is input on scl. start and stop conditions are recognized as the beginning and end of a serial transfer. slave address a control byte is the first byte r eceived following the start condition from the master device. the control byte consists of a four bit control code; for the ds1624, this is set as 1001 binary for read and write operations. the next three bits of the control byte are the device select bits (a2, a1, a0). they are used by the master device to select which of eight devices are to be accessed. these bits are in effect the three least significant bits of the slave address. the last bit of the control byte (r/ w ) defines the operation to be performed. when set to a ?1?, a read operation is selected, when set to a ?0?, a write operation is selected. following the start condition the ds1624 monitors the sda bus checking the device type identifier being transmitted. upon receiving the 1001 code and appropriate device select bits, the slave device outputs an acknowledge signal on the sda line. 2- wire serial communication with ds1624 figure 3 ds1624 6 of 20 operation- measuring temperature a block diagram of the ds1624 is shown in figure 1. the ds1624 measures temperatures through the use of an on ? board proprietary temperature measurement technique. a block diagram of the temperature measurement circuitry is shown in figure 4. the ds1624 measures temperature by counting the number of clock c ycles that an oscillator with a low temperature coefficient goes through during a gate period determined by a high temperature coefficient oscillator. the counter is preset with a base count that corresponds to ?55 c. if the counter reaches zero before th e gate period is over the temperature register, which is also preset to the ?55 c value, is incremented indicating that the temperature is higher than ?55c. at the same time, the counter is preset with a value determined by the slope accumulator circuitr y. this circuitry is needed to compensate for the parabolic behavior of the oscillators over temperature. the counter is then clocked again until it reaches zero. if the gate period is still not finished, then this process repeats. the slope accumulator is used to compensate for the nonlinear behavior of the oscillators over temperature, yielding a high resolution temperature measurement. this is done by changing the number of counts necessary for the counter to go through for each incremental degree in temperature. to obtain the desired resolution, both the value of the counter and the number of counts per c (the value of the slope accumulator) at a given temperature must be known. ds1624 7 of 20 temperature measuring circuitry figure 4 internally, this calculation is performed by the ds1624 to provide 0.03125 c resolution. the temperature reading is provided in a 13 ? bit, two?s complement reading by issuing read temperature command. table 2 describes the exact relationship of output data to measured temperature. the data is transmitted serially through the 2 ? wire serial interface, msb first. the ds1624 can measure temperature over the range of -55 c to +125 c in 0.03125 c increments. for fahrenheit usage a lookup table or conversion factor must be used. temperature/data relationships table 2 temp digital output (binary) digital output (hex) +125?c 01111101 00000000 7d00h +25.0625?c 00011001 00010000 1910h +??c 00000000 10000000 0080h 0?c 00000000 00000000 0000h - ??c 11111111 10000000 ff80h - 25.0625?c 11100110 11110000 e6f0h - 55?c 11001001 00000000 c900h since data is transmitted over the 2 ? wire bus msb first, temperature data may be written to/read from the ds1624 as either a single byte (with temperature resolution of 1 c) or as two bytes, the second byte containing the value of the 5 least significant bits of the temperature reading as shown in table 1. note that the remaining three bits of this byte are set to all 0?s. slope accumulator preset compare low temperature coefficient oscillator counter preset =0 temperature register high tem perature coefficient oscillator counter =0 inc stop set/clear lsb ds1624 8 of 20 temperature is represented in the ds1624 in terms of a 0.0 3125 c lsb, yielding the following 13 ? bit format: operation and control a configuration/status register is used to determine the method of operation of the ds1624 will use in a particular application as well as indicating the status of the temperature con version operation. the configuration register is defined as follows: configuration/status register where done = conversion done bit. ?1? = conversion complete, ?0? = conversion in progress. 1shot = one shot mode. if 1shot is ?1?, the ds1624 will perform one temperature conversion upon receipt of the start convert t protocol. if 1shot is ?0?, the ds1624 will continuously perform temperature conversions. this bit is nonvolatile and the ds1624 is shipped with 1shot = ?0?. since the configuration regi ster is implemented in e 2 , writes to the register require 10 ms to complete. after issuing a command to write to the configuration register, no further accesses to the ds1624 should be made for at least 10 ms. operation ? memory byte program mode in this mode, the master sends addresses and one data byte to the ds1624. following a start condition, the device code (4 ? bit), the slave address (3 bit), and the r/ w bit, which is logic low, are placed onto the bus by the master. the maste r then sends the access memory protocol. this indicates to the addressed ds1624 that a byte with a word address will follow after it has generated an acknowledge bit. therefore, the next byte transmitted by the master is the word address and will be writte n into the address pointer of the ds1624. after receiving the acknowledge of the ds1624, the master device transmits the data word to be written into the addressed memory location. the ds1624 acknowledges again and the master generates a stop condition. th is initiates the internal programming cycle of the ds1624. a repeated start condition, instead of a stop condition, will abort the programming operation. during the programming cycle the ds1624 will not acknowledge any further accesses to the device until the programming cycle is complete (approximately 10 ms.) 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 lsb = +25.0625c msb done 1 0 0 1 0 1 1shot ds1624 9 of 20 page program mode to program the ds1624 the master sends addresses and data to the ds1624 which is the slave. this is done by supplying a start condition followed by the 4 ? bit device code, the 3 ?bi t slave address, and the r/ w bit which is defined as a logic low for a write. the master then sends the access memory protocol. this indicates to the addressed slave that a word address will follow. the slave outputs the acknowledge p ulse to the master during the ninth clock pulse. when the word address is received by the ds1624 it is placed in the address pointer defining which memory location is to be written. the ds1624 will generate an acknowledge after every 8 ? bits received and s tore them consecutively in an 8 ? byte ram until a stop condition is detected which initiates the internal programming cycle. a repeated start condition, instead of a stop condition, will abort the programming operation. during the programming cycle the ds1624 will not acknowledge any further accesses to the device until the programming cycle is complete (approximately 10 ms). if more than 8 bytes are transmitted by the master the ds1624 will roll over and overwrite the data beginning with the first receive d byte. this does not affect erase/ write cycles of the eeprom array and is accomplished as a result of only allowing the address register?s bottom 3 bits to increment while the upper 5 bits remain unchanged. the ds1624 is capable of 50,000 writes (25,000 erase/write cycles) before eeprom wear out may occur. if the master generates a stop condition after transmitting the first data word, byte programming mode is entered. read mode in this mode, the master is reading data from the ds1624 e 2 memory. the mas ter first provides the slave address to the device with r/ w set to ?0?. the master then sends the access memory protocol and, after receiving an acknowledge, then provides the word address, which is the address of the memory location at which it wishes to begin reading. note that while this is a read operation the address pointer must first be written. during this period the ds1624 generates acknowledge bits as defined in the appropriate section. the master now generates another star t condition and transmits the slave address. this time the r/ w bit is set to ?1? to put the ds1624 in read mode. after the ds1624 generates the acknowledge bit it outputs the data from the addressed location on the sda pin, increments the address pointer, and, if it receives an acknowledge from the master, transmits the next consecutive byte. this auto - increment sequence is only aborted when the master sends a stop condition instead of an acknowledge. when the address pointer reaches the end of the 256 ? byte memory space (address ffh) it will increment from the end of the memory back to the first location of the memory (address 00h). command set data and control information is read from and written to the ds1624 in the format shown in figure 3. to write to the ds1624, the master will issue the slave address of the ds1624 and the r/ w bit will be set to ?0?. after receiving an acknowledge the bus master provides a command protocol. after receiving this protocol the ds1624 will issue an acknowledge then the master may send data to the ds1624. if the ds1624 is to be read, the master must send the command protocol as before then issue a repeated start condition and the control byte again, this time with the r/ w bit set to ?1? to allow reading of the data from the ds1624. the command set for the ds1624 as shown in table 3 is as follows: ds1624 10 of 20 access memory [17h] this command instructs the ds1624 to access its e 2 memory. after issuing this command, the next data byte is the value of the word address to be accessed. see operation ? memory section for detailed explanations of the use of this protocol and data format following it. access config [ach] if r/ w is ?0?, this command writes to t he configuration register. after issuing this command, the next data byte is the value to be written into the configuration register. if r/ w is ?1?, the next data byte read is the value stored in the configuration register. read tem perature [aah] this command reads the last temperature conversion result. the ds1624 will send two bytes in the format described earlier, which are the contents of this register. start convert t [eeh] this command begins a temperature conversion. no further data is required. in one ? shot mode the temperature conversion will be performed and then the ds1624 will remain idle. in continuous mode this command will initiate continuous conversions. stop convert t [22h] this command stops temperature conversion. no further data is required. this command may be used to halt a ds1624 in continuous conversion mode. after issuing this command, the current temperature measurement will be completed then the ds1624 will remain idle until a start convert t is issued to re sume continuous operation. ds1624 command set table 3 instruction description protocol 2 - wire bus data after issuing protocol notes temperature conversion commands read temperature reads last converted temperature value from temperature regi ster. aah ds1624 11 of 20 during the programming cycle the ds1624 will not acknowledge any further accesses to the device until the programming cycle is complete (approximately 10 ms). memory function example bus master mode ds1624 mode data (msb first) comments notes {command protocol for configuration register} {start here} tx rx start bus master initiates a start condition. tx rx ds1624 12 of 20 r x tx ds1624 sends the lsb byte of temperature. bus master mode ds1624 mode data (msb first) comments notes tx rx nack bus master sends ?no acknowledge? bit. tx rx stop bus master initiates the stop condition. {command protocol for writing to eeprom} {start here} tx rx start bus master initiates a start condition. tx rx ds1624 13 of 20 rx tx ds1624 sends the first byte of data. tx rx ack bus master g enerates acknowledge bit. ds1624 14 of 20 bus master mode ds1624 mode data (msb first) comments notes rx tx ds1624 sends the second byte of data. tx rx ack bus master generates acknowledge bit. . . . . . . . . . . . . . . . . rx tx ds1624 sen ds the n - th byte of data. 5 tx rx nack bus master send ?no kwowledge? bit. tx rx stop bus master initiates the stop condition. notes: 1. if this protocol follows a write and the ds1624 does not acknowledge here, restart the protocol at the start here. if it does acknowledge, continue on. 2. wait for write to complete (10 ms typ. 50 ms max). if ds1624 does not acknowledge the command protocol immediately following a configure register or write mem protocol, the ds1624 has not finished writing. restart the new command protocol until the ds1624 acknowledges. 3. if n is greater than eight, the last eight bytes are the only bytes saved in memory. if the starting address is 00 and the incoming data is 00 11 22 33 44 55 66 77 88 99, the result will be mem00=88 mem0 1=99 mem02=22 mem03=33 mem04=44 mem05=55 mem06=66 mem07=77. the data wraps around and overwrites itself. 4. the stop condition causes the ds1624 to initiate the write to eeprom sequence. if a start condition comes instead of the stop condition, the write is aborted. the data is not saved. 5. for reading, the address is incremented. if the starting address is 04h and 30 bytes of data are read out, 21h is the final address read. ds1624 15 of 20 absolute maximum ratings* voltage on any pin relative to ground ............................................................................... -0.5v to +6.0v opera ting temperature range ........................................................................................... -55 c to +125 c storage temperature range .............................................................................................. -55 c to +125 c soldering temperature (reflow) ....................................................................................................... +260 c lead temperature (soldering, 10s) ................................................................................................... +300 c * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions parameter symbol min typ max units notes supply voltage v dd 2.7 5.0 5.5 v 1 dc electrical characteristics (- 55c to +125c; v dd =2.7v to 5.5v) parameter symbol condition min typ max units notes thermometer error t err 0c to 70c -55c to +0c and +70c to +125c ? c 10 see typical curve lo w level input voltage v il - 0.5 0.3v dd v high level input voltage v ih 0.7v dd v dd + 0.5 v pulse width of spikes which must be suppressed by the input filter t sp fast mode 0 50 ns low level output voltage v ol1 3 ma sink current 0 0.4 v v ol2 6 ma sink current 0 0.6 v input current each i/o pin 0.4 ds1624 17 of 20 ac electrical characteristics (- 55c to +125c; v dd =2.7v to 5.5v) parameter symbol min typ max units notes input capacitance c i 5 pf notes: 1. all voltages are referenced to ground. 2. i/o pins of fast mode devices must not obstruct the sda and scl lines if v dd is switched off. 3. i cc specified with sda pin open. 4. i cc specified with v cc at 5.0v and sda, scl = 5.0v, 0 c to 70c. 5. after this period, the first clock pulse is generated. 6. the maximum t hd:dat has only to be met if the device does not stretch the low period (t low ) of the scl signal. 7. a fast mode device can be used in a standard mode system, but the requirement t su:dat > 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax +t su:dat = 1000+250 = 1250 ns before the scl line is released. 8. c b ? total capacitance of one bus line in pf. 9. writing to the nonvolatile memory should only take place in the 0c to 70c temperature range. 10. see typical curve for specification limits outside the 0c to 70c temperature range. thermometer error reflects sensor accuracy as tested during calibration. ds1624 18 of 20 timing diag ram note: the ds1624 does not delay the sda line internally with respect to scl for any length of time typical performance curve ds1624 digital thermometer and thermostat temperature reading error temperature (deg. c) t sp ds1624 19 of 20 package information for the latest package outline information and land patterns, go to www.maxim - ic.com/packages . note that a ?+?, ?#?, or ? - ? in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 8 pdip p8+4 21 - 0043 ? 8 so w8+2 21-0262 90-0258 ds1624 20 of 20 revision history revision date description pages changed 5/12 updated ordering information, soldering, and package information 1, 2, 7, 14, 18 |
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